1. Field of the Invention
The present invention relates to divide-by-m counters for generating a lower frequency output clock signal from a higher frequency source clock signal.
2. Description of Prior Art
Most of the prior art counter schemes only give a fifty per cent duty cycle waveform if the number of the count m (number of cycles of the source clock to a single cycle of the output clock) is an even number. If the count m is an odd number, typically an output clock signal will have a high state that will be (m+1)/2 counts and a low state that will have (m-1)/2 counts. Those designs that accommodate an odd numbered m and also have a fifty percent duty cycle, have unnecessary complexity and delays.